The disclosure relates generally to semiconductor chips and more specifically to methods, systems, and structured for forming on-chip passwords.
On-chip password or chip identification has become increasingly important, particularly with the proliferation of Internet of things (IoT). The application of on-chip password can be used for access authentication and/or to prevent counterfeits. On-chip password can be software based or hardware-based. However, a software-based password is susceptible to cyberattack. A hardware-based password is typically achieved by using eFuse (electrical fuse) or by using embedded flash memory (eFlash). However, both methods have drawbacks. Although eFuse is typically CMOS compatible (for old CMOS nodes), one problem with eFuse is that it can only be used once. In other words, one cannot flexibly change the password. Thus, for the state-of-the-art CMOS, which use high-k/metal gates, the conventional eFuse can no longer be obtained without additional process steps. In contrast to eFuse, eFlash can be re-programmed multiple times. However, the eFlash process is not compatible with the conventional CMOS.
Therefore, it would be desirable to have a method and apparatus that take into account at least some of the issues discussed above, as well as other possible issues. For example, it would be desirable to have a method and apparatus that overcome a technical problem with forming an on-chip password that can be fabricated along with CMOS and that can be programmed multiple times.